ASIC Power Engineer, Silicon @ Google

Job Description

Minimum qualifications: Bachelor's degree or equivalent practical experience. 5 years of experience in ASIC power management or low power design/methodology. Experience with ASIC low power flows and power management concepts. Preferred qualifications: Master's degree or PhD in Electronics, Computer Engineering, or Computer Science. Experience with low power architectures and power optimization techniques (e.g., voltage domain design, clock gating, power gating, Dynamic Voltage Frequency Scaling). Experience with ASIC power modeling and estimation, defining power goals, power management IP and sensors, peak power management/detection/mitigation, in-rush current, adaptive clock distribution, techniques for power/voltage domains design, or competitive power analysis. Experience in Fabric, MultiMedia, and ISP. About The Job Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team. designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Define and drive solutions for Google SoCs to optimize Power-Performance-Area (PPA) under peak current and thermal constraints. Define power KPIs and SoC/IP-level power goals, guide architecture, design, and implementation to achieve power goals and track power throughout the design cycle. Propose and drive power optimizations throughout the design process from concept to mass production. Perform algorithm development, modeling and analysis of various low power approaches, and perform post-silicon characterization and production of power features. Drive power-performance trade-off analysis for engineering reviews and product roadmap decisions.

Employement Category:

Employement Type: Full time
Industry: IT - Hardware / Networking
Role Category: IT - Hardware / Networking
Functional Area: Not Applicable
Role/Responsibilies: ASIC Power Engineer, Silicon

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Keyskills:   sensors Fabric MultiMedia ISP circuit design system design algorithm development modeling ASIC power management low power designmethodology low power flows power management concepts low power architectures power optimization techniques ASIC power modeling defining power goals power management IP peak power management inrush current adaptive clock distribution postsilicon characterization