Your browser does not support javascript! Please enable it, otherwise web will not work for you.

Design Verification Engineer @ Agasthya App Labs

Home > Embedded, VLSI

 Design Verification Engineer

Job Description

Company: Agasthya App Labs

Desgnation: Design Verification Engineer

Skill Set: SOC/IP Verification

Methodology: SV,UVM

Protocols: Ethernet,USB,PCLE,MIPI

Experience: 3.5-10 years

Location: Pune,Ahmedabad,Bangalore

If anyone interested,please send me updated CV to mail id - ap*****n@ag************s.com

or

contact - 7794067***

Employement Category:

Employement Type: Full time
Industry: Engineering / Construction
Role Category: Embedded, VLSI
Functional Area: Not Applicable
Role/Responsibilies: Design Verification Engineer

Contact Details:

Company: Agasthya App Labs
Location(s): Bengaluru

+ View Contactajax loader


 Job seems aged, it may have been expired!
 Fraud Alert to job seekers!

₹ 2.5 - 6 Lakh/Yr

Agasthya App Labs

Agasthya is a Semiconductor, Embedded Systems and IOT provider company which is a highflier in implementing Digital Transformation.  We offer a wide-ranging portfolio of services to boost the overall productivity and also the value of the clients’ software, Semiconductor, Embedded Systems IOT a...