Job Description
Company:Qualcomm India Private Limited
Job Area:Engineering Group, Engineering Group > Hardware Engineering
Job Overview:Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in.
GENERAL SUMMARYJob Role
* Work with multiple SOC Design teams to rollout robust Logic Synthesis, UPF synthesis, QoR optimization and netlist Signoff flows
* Provide implementation flows support and issue debugging services
to SOC design teams across various site
* Develop and maintain 3rd party tool integration and product
enhancement routines
* Should lead implementation flow development effort independently by working closely with design team and EDA vendors
* Should drive new tool evaluation, methodology refinement for PPA optimization
Skill Set
* Proficiency in Perl/Python/Tcl
* Familiar with Synthesis tools (DC/FC/Genus), LEC, LP signoff tools
* Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking
* Familiarity with standard software engineering practices like Version
Control, Configuration Management, Regression is a plus
* Should be sincere, dedicated and willing to take up new challenges
Experience
3 to 6 years of experience in RTL,UPF & Physical aware Synthesis for cutting edge technology nodes, logic equivalence checking, Scripting and Netlist Timing Signoff
Job Role* Work with multiple SOC Design teams to rollout robust Logic Synthesis, UPF synthesis, QoR optimization and netlist Signoff flows
* Provide implementation flows support and issue debugging services
to SOC design teams across various site
* Develop and maintain 3rd party tool integration and product
enhancement routines
* Should lead implementation flow development effort independently by working closely with design team and EDA vendors
* Should drive new tool evaluation, methodology refinement for PPA optimization
Skill Set* Proficiency in Perl/Python/Tcl
* Familiar with Synthesis tools (DC/FC/Genus), LEC, LP signoff tools
* Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking
* Familiarity with standard software engineering practices like Version
Control, Configuration Management, Regression is a plus
* Should be sincere, dedicated and willing to take up new challenges
Experience3 to 6 years of experience in RTL,UPF & Physical aware Synthesis for cutting edge technology nodes, logic equivalence checking, Scripting and Netlist Timing Signoff
Minimum QualificationsEducation:Work Experiences:Certifications:Skills:Preferred QualificationsEducation:Work Experiences:Certifications:Skills:Applicants: If you need an accommodation, during the application/hiring process, you may request an accommodation by sending email to (mailto:[Confidential Information]subject=Accommodation%20Support)
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If you would like more information about this role, please contact Qualcomm Careers (http://www.qualcomm.com/contact/corporate).
Employement Category:
Employement Type: Full time
Industry: IT
Functional Area: IT
Role Category: Software Engineer
Role/Responsibilies: PD Synthesis Sr Engineer
Contact Details:
Company: Qualcomm
Location(s): Noida, Gurugram
Keyskills:
PD Synthesis Sr Engineer