6 t o 10 years of experience in Signoff Timing Analysis with a good understanding of Physical Design flow.
Hands on experience in timing closure of high-performance processor cores.
Good understanding of constraints
Strong understanding of CMOS circuit design
Proficiency with Cadence Synopsys STA tools
Familiarity with ECO generation tools - DMSA, Tweaker
Experience in Perl, TCL, python and shell scripting is desirable
Experience with HSPICE desirable
Keyskills: STA Timing closure Hardware engineering Staffing Circuit designing Shell scripting Perl Python Physical design Recruitment
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