ASIC/Layout Design Engr, II @ Synopsys

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ASIC/Layout Design Engr, II

Synopsys
5 - 8 Years
India
4 years ago
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Job Description

You will be part of a strong development team in the area of GPIOs , Speciality IOs and General Purpose Analog IPs
You will develop layouts designs for Analog Full Custom IPs such as
GPIOs , I2C, I3C , SMBUS , eMMC , SVID , Quad SPI , JTAG
High performance LVDS
Crystal Oscillators
On-Chip Thermal and Voltage Sensor , Adaptive Bias Generator , Process Monitoring Block, Voltage Regulators
You will be working with experienced set of teams locally and in with people from various sites spread across globe.
Technical Attributes
5+ years of industry experience in related field
Good grip over CMOS circuit layout fundamentals, Technology effects, IO frame design methodology, Analog matching concepts
Should have good understanding of layout and parasitic extraction.
Should have good grip over automation /scripting languages
Can provide technical guidance to juniors for good quality layout
Personal Attributes
Has a strong desire to learn and explore new technologies.
Demonstrates good analysis and problem-solving skills.
High energy individual with the ability to go an extra mile.
A proactive team player with good written and verbal communication skills.
Networks with senior internal and external personnel in own area of expertise.

Employement Category:

Employement Type: Full time
Industry: Full time
Functional Area: Not Applicable
Role Category: IT
Role/Responsibilies: ASIC/Layout Design Engr, II

Contact Details:

Company: Synopsys India
Location(s): India

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Write briefly about yourself, your experience and education (*)

Attach ResumeMax 2.38 MB (RTF, PDF, DOC, DOCX formats only parsed)

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Synopsys

Synopsys, Inc. (Nasdaq:SNPS) is a world leader in delivering semiconductor design software, intellectual property (IP), design for manufacturing (DFM) solutions and professional services that companies use to design systems-on-chips (SoCs) and electronic systems. The company?s products enable semico...

ASIC/Layout Design Engr, II @ Synopsys

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