Top3 Semiconductor Organization in the world
Design Verification Manager/ Lead ( IP )
We are looking for IP verification with min 6yrs to 16 years of experience.,
Kindly share the resumes with me over email.
Our team is part of group which verifies IPs that are going into FPGAs. We have IPs like 5G, DDR, , MIPI, Ethernet, ANLT and PCIE for which we are hiring. These are new teams that we are building so we are looking to hire people across the experience spectrum for roles from individual contributors to leads. We use SystemVerilog with UVM methodology.
As part of Group delivers high-quality, timely, and differentiating FPGA solutions to our customers. In line with that, we are looking for a Design Verification Engineer to join our dynamic and growing team.
You will work closely with design teams to architect effective and efficient testbench and verification strategies to promote effective debug and failure detection; build UVM infrastructure including monitors, drivers, and scoreboards; produce functional coverage and code coverage; monitor dashboards and regressions; analyze root cause; develop constrained random stimulus and shape content to effectively stress the design space; and create test plans to ensure functional correctness.
Qualifications:
You must possess the minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Preferred Qualifications:
Contact: Uday Bhaskar
Mulya Technologies
"Mining the Knowledge Community"
Email id : mu**********r@ya**o.com
Keyskills: Sv mipi ovm PCIE ddr6 rtl ddr4 UVM ddr5 5G Ddr Ethernet System Verilog
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