Signal Integrity Engineer @ Juniper Networks

• Contribute in a centralized SI team that supports next generation cutting edge technologies.
• Responsible for delivering system level signal integrity solutions for large complex high speed systems, boards & packages
• Take ownership on all aspects of signal integrity design, ranging from design feasibility to product validation
• Develop SI rules, build on design guides & checklists, review design implementation, create test plans, document characterization & measurement reports
• Improve & optimize design margins through interconnect, timing & xtalk analysis, 3D EM & channel simulations for high speed designs
• Understand SI trade-offs, impact of various aspects of system design, provide timely technical assessments & progress updates to SI Management.
• Design & characterize test structures & channel models to correlate simulations & measurements for serdes & interconnects .

Preferred skills & experience:

• Bachelors / Masters degree in Electronics / Electrical engineering or equivalent
• Self-motivated, ability to contribute independently as well as in a team environment that is matrixed and spread across geography.
• Self-learner, Strong problem solving, board & system level lab bring up, debugging & characterization skills
• Excellent oral & written communication skills, capable of presenting concepts, analysis & updates to larger teams and forums
• Knowledge of Electromagnetics & Transmission line concepts, reflection & terminations, timing & jitter, crosstalk & noise, channel modelling & serdes equalizations, PDN & decoupling
• Familiarity with PCB stack up design, best practices, trade-offs in line geometries, PCB materials & surface finishes, vendor capabilities & Mfg process.
• Experience with lab equipments such as high bandwidth real time & sampling Oscilloscopes, phase noise analysers, TDR, VNA, spectrum analysers.
• Proficient with simulation and analysis tools like ADS, HFSS, HSPICE, Sisoft QSI, QCD, Cadence Allegro, Sigrity, PowerSI, MATLAB, etc
• Experience with common SI simulation models such as IBIS, IBIS-AMI, S-parameter, COM analysis, etc
• Knowledge of interface standards such as DDR 3/4, PCIe gen 2/3, 10GKR, SATA, XFI, XAUI, CAUI, CDAUI etc
• Experience with 56G PAM4, 25G & 10G NRZ serdes technologies - simulation, bring up, debug, measurements, optimization a plus.