IP DV profile - C++ Team lead @ Nesflair

  Location : Hyderabad / Bangalore

                 EDUCATION:

•         Masters in VLSI/ECE/EE with relevant course work and project background with 7+ years of experience, or Bachelors with 9+ years of experience

                  RESPONSIBILITIES:

•         Lead a DV team of ~6-7 members.
•         Responsible for Front-End design verification.
•         Responsible for DTP creation.
•         Work in collaboration with Design/RTL Engineers.

REQUIREMENTS:

•         Experience in complex ASIC Design.
•         Experience in development of TB components in UVM/SV & C++.
•         Direct experience in SOC or Audio verification is plus.
•         Experience in assertion based verification.
•         Experience in Functional and Code coverage.
•         Should have proficiency in flow development and scripting.
•         Experience in FPGA DV is a plus.
•         Expertise in Perl and Tcl is a plus.
•         Should be able to work closely with RTL Designers.
•         Must have good communication & Analytical thinking skills.
•         Knowledge of chip bus interfaces such as AXI and various standard peripherals & interfaces such as APB, AHB is a plus.
•         Must have good communication skills and the ability and desire to foster a team environment.

+ View Contact

Keyskills:   complex ASIC Design UVM/SV & C++ SOC FPGA DV RTL Designers.