Lead Physical Floorplan and Integration Engineer
Top2 Semiconductor Organization in the world
Location: Bangalore / Hyderabad
Job Description:
Our Foundry Services will be differentiated from other Foundry offerings with a combination of leading-edge packaging and process technology, committed capacity in the US and Europe - available for customers globally -
We are looking for Senior floorplan and integration engineer to drive our High-Performance Computing Product line. The responsibilities include driving the definition of Chip Floorplan in Close Collaboration with RTL, Development of Bump File, Physical Partitioning and planning including Channels, Abutments, Feedthroughs and SoC integration for seamless tapeout.
Right Candidate will bring-in 10+ years of in-depth technical experience in high-end SOC level/Subsystem Level Fullchip execution on Chips Such as Server CPUs/SOCs, Graphics SOCs or SOCs in AI Space. She/he should have in-depth understanding of floor-planning and integration in Advanced process technologies working closely with RTL, PDN, Clocking, IP and Packaging teams. The person should have good leadership skills, right mindset and ability to handle dynamic changes in RTL. Automation skills in TCL/Perl/Python and Design Flow understanding is a major plus. Excellent debugging skills, Team work, professionalism and communications are a must.
Qualifications:
Bachelors/Masters degree in Electronics/Computer Science required with 10+ years' experience
Contact: Uday Bhaskar
Mulya Technologies
"Mining the Knowledge Community"
Email id : mu**********r@ya**o.com
Keyskills: Physical Design floorplanning soc full chip synopsys cadence
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