Senior Engineer ANT Layout @ Micron

Job Description

Our vision is to transform how the world uses information to enrich life for all.
Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing.JR17974 Senior Engineer ANT LayoutResponsibilities will include, but are not limited to:

• Ability to do memory array and pitch layout development in cutting edge memory technology
• Close interaction and collaboration with the Design Rule and Process Integration teams to define next generation array and pitch circuitry such as 3D memory core, WL drivers and connectivity, page buffers, sense amplifier, decoders, etc.
• Work with design leads to plan/drive chip level routing plan connecting to the array/pitch circuits.
• This individual must be a self-starter and exhibit clear verbal and nonverbal communication skills.
• They must demonstrate a strong ability to debug problems, find effective solutions, and negotiate with the engineering staff.
• They must demonstrate a high level of technical competence.
• They will interact with the engineering staff to create any of the layout blocks from schematics and verify the integrity of the data.
• You will organize and prioritize logistics to meet scheduled deadlines, and proactively develop methodologies for issue resolution.
• Individual is responsible for coordinating with process integration, design, and layout to deliver on schedule with quality.
• Communicate effectively across functional groups e.g. process integration, design, verification, and CAD.
• Good understanding of design rules and deliver with quality layout.

Job Requirements

• 5 to 8 years of experience in layout and equivalent related education.
• Understanding of layout methodology from initial chip plan to tapeout.
• Experience in array or pitch layout is a must.
• Experience in 3D array layout is a plus.
• Strong debug and problem-solving skills for LVS, DRC and layout issues without much supervision.

Skills and Knowledge

• Experience with Cadence tool is a must.
• Experience with VXL.
• Experience in using Calibre tool.
• A self-starter who is pro-active and capable of leading when needed.
• Excellent verbal and written communication skills required.
• Independent with strong analytical skills, creative thinking and self-motivated.
• Capable of working in a cross functional multi site team environment.

Employement Category:

Employement Type: Full time
Industry: Semiconductor
Functional Area: IT
Role Category: Software Engineer
Role/Responsibilies: Senior Engineer ANT Layout

Contact Details:

Company: Micron
Location(s): Hyderabad

+ View Contact