Interface with design team to ensure DFT design rules and coverages are met.
Generating high quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models through the use of on-chip test compression techniques.
MBIST verification (including repair), test pattern generation through Mentor tool.
ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations.
Work with the Product/Test engineering teams on the delivery of manufacturing test patterns for ATE.
Minimum Qualifications:
Be a member of the team that plays a significant role in ensuring the quality of Connectivity SoCs through structured DFT, Automatic Test Pattern Generation (ATPG) and Memory Built-In Self-Test (MBIST) techniques.
BE with minimum of 1 years exp
Job Classification
Industry: Electronic Components / Semiconductors Functional Area: Other, Role Category: Other Role: Other Employement Type: Full time
Education
Under Graduation: Any Graduate Post Graduation: Any Postgraduate Doctorate: Any Doctorate