Graphics Sr. Staff design Engineer - Mumbai
- Qualcomm
- 8 - 10 years
- Mumbai
- 3 years ago
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Job Description
General Summary:
- 8-10 years of experience in ASIC - Physical aware synthesis/STA closure.
- Expertise with STA with prime time / Tempus
- Good Experience in synthesis timing closure and interactions with Design / DFT and PD.
- Knowledge of low-power techniques like clock gating, power gating and MV designs.
- Expertise in Formal verification with Conformal LEC / Synopsys Formality.
- Experience in Low power flows for CLP, UPF ( Cadence low power, Unified power format)
- Expertise in Synopsys/Cadence Synthesis tools
- Good experience in ECO flows
- Experience in Spyglass Lint/CDC checks and waiver creation
- Experience in RTL HDL languages Verilog/VHDL
- Understanding of RTL to GDS flow
- Expertise in Perl, TCL language
- Good knowledge or understanding of Physical design and their steps.
Job Classification
Industry: Electronic Components / SemiconductorsFunctional Area: Other,
Role Category: Other
Role: Other
Employement Type: Full time
Education
Under Graduation: Any GraduatePost Graduation: Any Postgraduate
Doctorate: MPHIL in Any Specialization, Ph.D/Doctorate in Any Specialization, Any Doctorate
Contact Details:
Company: Qualcomm TechnologiesLocation(s): Mumbai
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Keyskills: Graphics HDL VHDL ASIC Timing closure DFT formal verification Verilog Perl Physical design
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