RF layout Engineer - Sr.Engineer @ Qualcomm

Role Responsibilities:

As a RF layout engineer, you will be responsible for:-

• Detailed transistor-level layout of RF and analog circuit blocks including LNA, mixers, PLL, ADC/DAC, bias/LDO, Driver and Tx blocks
• Proven hands-on experience in layout design and methodology development.
• Efficient programming skills in scripting languages like SKILL etc
• Block level and Super blocks level layout through full verification flow including extraction, DRC, LVS, and DFM checking
• Co-work with designers across geographies on block level and top-level floor planning
• Layout review for power/ground routing, electro migration, signal path check, differential and IQ matching, and signal coupling-
• Top-level layout integration and verification

Key Qualifications:

• Experience in custom RF/analog layout with extensive knowledge of deep sub-micron CMOS (14nm FinFET and below)
• Knowledgeable in layout techniques for device matching, minimizing parasitic, RF shielding, and high frequency routing
• Solid understanding of RC delay, electro migration, and coupling
• Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD, WPE, etc.
• High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc.
• Knowledge of CADENCE layout tools
• Excellent communication skills and able to work with cross-functional teams
• Capability to lead other layout engineers for top-level integration
• Ability to recognize failure prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems
• Scripting skills in PERL or SKILL are a plus.

Educational Qualification:

• B.E /B.Tech or M.E/MTech in Electrical and Electronics are preferred.

Minimum Qualifications:

1. Should be well versed with floor planning, routing till verification.

2. Knowledge of programming language like Skill is Plus.