SOC DFT DV Requirement
Exp- 5 to 10 yrs
Location- Bangalore
Np- 15days to Immediate
What are the responsibilities in this role
Develop and execute pre-silicon verification test plans for DFT features of the chip. Develop directed and random verification tests to validate the functionality.
Verify DFT design blocks and subsystems (such as MBIST, high speed IO PHY, fuse, clocks, reset) using complex SV or C++ verification environments. Construct SystemVerilog and/or C/C++ models and test sequence libraries for simulation.
Debug regression test failures to expose specification and implementation issues. Identify and address areas of concern to meet design quality objectives.
Post silicon ATE and System level debug support of the test patterns delivered. Optimize the test patterns to improve the test quality and reduce test costs.
What is the experience and knowledge you should have
5 year experience in DFT feature verification (such as JTAG, MBIST, SCAN, fuse, IO-PHY loopback testing)
Strong programming skills in Verilog and/or C++
Strong debug skills and experience with debug tools such as Verdi.
Experience with EDA simulation tools like Synopsys VCS, Cadence NCSIM, Verdi
Experience with any scripting languages like Tcl/Perl/Ruby/Python
Working knowledge of Unix/Linux OS, file version control.
What educational background should have
Minimum Engineering Degree in Electronics/Electrical/Computer Science
Keyskills: python tcl scripting dft jtag c++ scan mbist fuse
Magna Infotech is a division of USD 400 + million Quess Group (quesscorp.com) which in turn is a subsidiary of USD 37+ billion - Canadian Multinational, Fairfax Financial Holding Group. Magna Infotech is the largest staff Augmentation and Solutions Company in India, USA and APAC regions. We are a ...