Lead FPGA Design Engineer Job in Incise @ Incise Infotech

Job Description

Use EDA tools like Xilinx Vivado, ModelSim, and MATLAB (DSP Blockset like FFT) for design, simulation, and debugging. Implement signal demodulation schemes such as BFM, FSK, BFSK, MSK, GFSK, GMSK, BPSK, QPSK, 8PSK, OQPSK, and QAM. Design and integrate decoding modules, including Bit De-Interleavers, HDB3 Decoders, and Forward Error Correction (FEC) algorithms such as Reed-Solomon. Develop solutions for de-scrambling, convolution decoding, and deframing for protocols like E1, E3, T1, and T3. Work with standards such as ATSC1, ATSC2, DVB-T/T2/H, and DTMB to deliver compliant FPGA designs.,

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Rs 0 - 50K PM Rs 50K - 1 LPA Rs 1.0 - 1.5 LPA Rs 1.5 - 2.0 LPA Rs 2.0 - 2.5 LPA Rs 2.5 - 3.0 LPA Rs 3.0 - 3.5 LPA Rs 3.5 - 4.0 LPA Rs 4.0 - 4.5 LPA Rs 4.5 - 5.0 LPA Rs 5 - 6 LPA Rs 6 - 7 LPA Rs 7 - 8 LPA Rs 8 - 9 LPA Rs 9 - 10 LPA Rs 10 - 12 LPA Rs 12 - 14 LPA Rs 14 - 16 LPA Rs 16 - 18 LPA Rs 18 - 20 LPA Rs 20 - 22 LPA Rs 22 - 24 LPA Rs 24 - 26 LPA Rs 26 - 28 LPA Rs 28 - 30 LPA Rs 30 - 32 LPA Rs 32 - 34 LPA Rs 34 - 36 LPA Rs 36 - 38 LPA Rs 38 - 40 LPA Rs 40 - 42 LPA Rs 42 - 44 LPA Rs 44 - 46 LPA Rs 46 - 48 LPA Rs 48 - 50 LPA Rs 50 - 75 LPA Rs 75 Lakh - 1C PA Rs 1 Crore+ PA

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Keyskills:   ModelSim MATLAB FFT BFM QPSK QAM E1 T1 T3