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Quest Global Hiring Physical Design Engineer

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 Quest Global Hiring Physical Design Engineer

Job Description

  • 4+ years of professional experience in physical design, preferably with high performance designs.
  • Experience in minimum one of the Full Chip Chip Integration activities such as Full Chip Floor Planning, Power Planning , Bus Planning, Full Chip timing, Full Chip Reliability and Full Chip Physical Verification is desirable.
  • Experience in FEC,VCLP.
  • Hands-on experience in developing and modifying PD-flow/EDA-tools scripts/recipes using TCL/SHELL/PYTHON programming languages.
  • Experience in developing PD metrics dashboard scripts for QOR tracking is a plus
  • Experience in modifying STA constraints to check timing closure feasibility
  • Experience in various clock implementation strategies (Multi-point CTS, Flex-H, Custom-CTS) for meeting block level and full chip level latency and skew targets
  • Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5/3nm

Please forward your updated profile to below details to ch****************u@qu*********l.com.


Job Classification

Industry: IT Services & Consulting
Functional Area / Department: Engineering - Hardware & Networks,
Role Category: Hardware
Role: Physical Design / Layout Engineer
Employement Type: Full time

Contact Details:

Company: Quest Global
Location(s): Hyderabad

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Keyskills:   STA PNR Timing Closure ICC Physical Design

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Quest Global

Synapse Quest Global is an industry leader & one among the fastest growing Service company in design services in the world and is the engineering backbone of most top tier Semiconductor and System companies around the world. Synapse Design target customers are companies with $1 billio...

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