Navneeth
DFT JD
The Role :
- As a key member of the LTTS DFT Team, the successful candidate will play a significant role in ensuring the quality of next generation through structural DFT, Automatic Test Pattern Generation (ATPG) and Memory Built-In Self-Test (MBIST) techniques.
Key Responsibilities :
- Working closely with the Architecture team and the various IP Design teams to align on the DFT requirements and successfully implementing the DFT RTL at the SoC level
- Set up DFT timing constraints, defining the overall SOC Test STA methodology.
- Working with the Design team to clean-up all the DFT related constraint issues
- Closely work with physical design team to generate and validate timing constraints
- Developing, improving, and maintaining automation scripts as necessary
Preferred Experience :
- Experience in DFT architecture for complex chips
- Exposure to Static timing analysis & Timing closure is required.
- Proven experience in DFT constraints handling, Block and Top-level test mode Static timing analysis (STA).
- Experience in SOC timing closure in DFT modes and sign-off
- Experience with RTL quality check tools/methodologies such as Spyglass, CDC, Lint is required.
- Must have experience with integration of various IPs into complex SOCs.
- Scan/ATPG patterns & test flows development, debug, test, and characterization
- Excellent hands-on debug skills and scripting skills are critical.
- Knowledge & experience of low power concepts, clock gating, power gating is a plus
- Experience with post-silicon bring up is a plus
- Any prior experience with microprocessor designs is a plus.
Qualification :
- B.E/B.Tech/M.E/M.Tech in Electrical/Electronic Engineering with 8+ years of DFT Experience
Contact details :
Navneeth
po*********************t@lt*s.com
7824800***
Keyskills:Â Â DFT JTAG Scan Insertion Atpg Bist Tetramax Mbist
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