Key Responsibilities:
Responsible for participating in the pre-silicon verification for full chip, blocks, multi-chip and system level verification
Power management and Power Gating (PG) verification
Specifying design verification plan at SOC level/IP level
Specifying or reviewing verification plans for complex blocks within the ASIC
Responsible for developing complex verification environment using the latest coverage/assertions based verification design methodology, which includes :
self-checking, reusable, automated verification environment : both at full-chip block level
Constrained random generators and reference models
Job Requirements and Skills:
B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering
Should have at least 5+ years experience in SOC verification.
Knowledge in processor based systems verification will be an advantage.
Experience in developing complex testbench/model in verilog, System verilog or SystemC
Develop cover points and perform coverage analysis.
Should have basic computer architecture understanding.
Experience in industry standard protocols verification is preferred
Expertise on low power verification (NLP/MVSIM/UPF/CPF)
Must have excellent knowledge of ASIC Design Flow
Keyskills: Graphics Power management System verilog Silicon high performance computing Windows Engineering Design ASIC Design Gaming
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