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Hiring Verification @ Foray Software

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 Hiring Verification

Job Description

Please find the Job description described below:

  • 5+ years of industry experience.
  • Create and enhance constrained-random and/or directed verification environments using System Verilog and UVM, or formally verify designs with SVA and industry leading formal tools.
  • Identify and write all types of coverage measures for stimulus quality measurements.
  • Debug tests with design engineers to deliver functionally correct design blocks.
  • Close coverage measures to identify verification holes.
Notice Period::ASAP

Share profiles to:sravani. wu*******i@fo******t.com

Job Classification

Industry: IT-Software, Software Services
Functional Area: IT Software - Application Programming, Maintenance,
Role Category: Programming & Design
Role: Programming & Design
Employement Type: Full time

Education

Under Graduation: Graduation Not Required, Any Graduate in Any Specialization
Post Graduation: Post Graduation Not Required, Any Postgraduate in Any Specialization
Doctorate: Any Doctorate in Any Specialization, Doctorate Not Required

Contact Details:

Company: Foray Software Pvt Ltd
Location(s): Hyderabad
Website: http://www.foraysoft.com/

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Keyskills:   UVM System Verilog

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₹ 9,00,000 - 19,00,000 P.A

Foray Software

Foray is a young, dynamic, small but rapidly growing information technology consulting and services company. Foray brings a well structured combination of business consulting, cutting edge products, customized solution development, and enterprise deployment expertise to generate game-changing value ...