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Verification Engineer - 4Yrs To 6Yrs @ Einfochips

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 Verification Engineer - 4Yrs To 6Yrs

Job Description

Roles and Responsibilities :

  • Minimum 3 to 4 years of experience in System Verilog HVL.
  • Minimum 2 to 3 years of experience in UVM.
  • Hands on experience of developing assertion, checkers, coverage and scenario creation.
  • Must have executed at-least 2 SoC Verification project
  • Experience in developing test and coverage plan, Verification environment and validation plan.

Knowledge of atleast one industry standard protocols like Ethernet, PCIe, MIPI, USB or similar is required.

Expertise in IP as well as SOC verification

Perl/shell scripting is a good to have

Perks and Benefits

As per company standards

Job Classification

Industry: Semiconductors, Electronics
Functional Area: IT Software - Embedded, EDA, VLSI, ASIC, Chip Design,
Role Category: Programming & Design
Role: Programming & Design
Employement Type: Full time

Education

Under Graduation: Any Graduate in Any Specialization, Graduation Not Required
Post Graduation: Post Graduation Not Required, Any Postgraduate in Any Specialization
Doctorate: Doctorate Not Required, Any Doctorate in Any Specialization

Contact Details:

Company: eInfochips Limited
Location(s): Ahmedabad
Website: https://www.einfochips.com

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Keyskills:   Validation USB Shell Scripting SOC Verification PCIE Perl System Verilog UVM

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Einfochips

eInfochips, an Arrow company, is a leading global provider of product engineering and semiconductor design services. With over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals. The company¢¢¢¢s serv...