Rtl Asic Design Front End Engineer/ Lead
- KnowledgeWorks Global
- 4 to 20 Yrs
- Other Karnataka
- 2 months ago
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Job Description
- Hi All, we are hiring RTL Engineer with Tessolve semiconductors - Bangalore, Hyderabad and Malaysia. Please find the below JD. JD 1: Design RTL ASIC Engineer/ Lead Location: Bangalore, Hyderabad Experience :- 4 to 20 Years Skills : RTL ASIC, CDC, Lint, integration, Micro-architecture , Timing &Synthesis, scripting (TCL/Perl/ Python) Experience and Skills Required 4 to 20 years of experience in SoC/IP Design. Expertise in Writing Detailed IP Specifications, Micro Architecture, IP design, Subsystem and SoC level integration. Expertise on RTL Development. Follow Coding Standards, expertise on Lint, CDC tools, Verification and Debugging of test cases, code and functional coverage analysis. In-depth knowledge of Clocking Methodology, Low Power Implementation. Hands on experience on writing constraints and exceptions, performing Synthesis, Timing Analysis and Design for Test Implementation. Experience of power partitioning and usage of CPF/UPF. Exposure to IP Design for ARM Microcontrollers based SoCs. Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB). Knowledge of one or more of the interface protocols, PCIe, DDR, Ethernet, I2C, UART, SPI. Experience in Matlab Simulations and Implementing Signal Processing IPs like Digital Filters, Math Functions or FFT engines. Experience in developing Security IPs for various Encryption standards. Experience in implementing On-chip Memory and Flash controllers. JD 2: Design RTL ASIC Design Engineer/ Lead Location: Malaysia Experience :- 5 to 8 Years Skills : RTL ASIC, integration , PCIE (Mandatory skills ) Experience and Skills Required 5 to 8 years of experience in SoC/IP Design. Expertise in Writing Detailed IP Specifications, Micro Architecture, IP design, Subsystem and SoC level integration. Expertise on RTL Development. Follow Coding Standards, expertise on Lint, CDC tools, Verification and Debugging of test cases, code and functional coverage analysis. In-depth knowledge of Clocking Methodology, Low Power Implementation. Hands on experience on writing constraints and exceptions, performing Synthesis, Timing Analysis and Design for Test Implementation. Experience of power partitioning and usage of CPF/UPF. Exposure to IP Design for ARM Microcontrollers based SoCs. Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB). Knowledge of one or more of the interface protocols, PCIe, DDR, Ethernet, I2C, UART, SPI. Experience in Matlab Simulations and Implementing Signal Processing IPs like Digital Filters, Math Functions or FFT engines. Experience in developing Security IPs for various Encryption standards. Experience in implementing On-chip Memory and Flash controllers. Kindly share updated CV to hidden_email or connect on hidden_mobile And Refer Disclaimer : ,
Employement Category:
Employement Type: Full timeIndustry: Engineering / Construction
Role Category: Not Specified
Functional Area: Not Specified
Role/Responsibilies: Rtl Asic Design Front End Engineer/ Lead/
Contact Details:
Company: TessolveLocation(s): Other Karnataka
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Keyskills: CDC Lint integration Microarchitecture PCIE
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